Using machine learning techniques to evaluate multicore soft error reliability

Virtual platform frameworks have been extended to allow earlier soft error analysis of more realistic multicore systems (i.e., real software stacks, state-of-the-art ISAs). The high observability and simulation performance of underlying frameworks enable to generate and collect more error/failurerelated data, considering complex software stack configurations, in a reasonable time. When dealing with sizeable failure-related data sets obtained from multiple fault campaigns, it is essential to filter out parameters (i.e., features) without a direct relationship with the system soft error analysis. In this regard, this paper proposes the use of supervised and unsupervised machine learning techniques, aiming to eliminate non-relevant information as well as identify the correlation between fault injection results and application and platform characteristics. This novel approach provides engineers with appropriate means that able are able to investigate new and more efficient fault mitigation techniques. The underlying approach is validated with an extensive data set gathered from more than 1.2 million fault injections, comprising several benchmarks, a Linux OS and parallelization libraries (e.g., MPI, OpenMP), as well as through a realistic automotive case study

Exploiting memory allocations in clusterized many-core architectures

Power-efficient architectures have become the most important feature required for future embedded systems. Modern designs, like those released on mobile devices, reveal that clusterization is the way to improve energy efficiency. However, such architectures are still limited by the memory subsystem (i.e., memory latency problems). This work investigates an alternative approach that exploits on-chip data locality to a large extent, through distributed shared memory systems that permit efficient reuse of on-chip mapped data in clusterized many-core architectures. First, this work reviews the current literature on memory allocations and explore the limitations of cluster-based many-core architectures. Then, several memory allocations are introduced and benchmarked scalability, performance and energy-wise, compared to the conventional centralized shared memory solution to reveal which memory allocation is the most appropriate for future mobile architectures. Our results show that distributed shared memory allocations bring performance gains and opportunities to reduce energy consumption

The impact of soft errors in memory units of edge devices executing convolutional neural networks

Driven by the success of machine learning algorithms for recognizing and identifying objects, there are significant efforts to exploit convolutional neural networks (CNNs) in edge devices. The growing adoption of CNNs in safety-critical embedded systems (e.g., autonomous vehicles) increases the demand for safe and reliable models. In this sense, this brief investigates the soft error reliability of two CNN inference models considering single event upsets (SEUs) occurring in register files, RAM, and Flash memory sections. The results show that the incidence of SEUs in flash memory sections tend to lead to more critical faults than those resulting from the occurrence of bit-flips in RAM sections and register files

Applying lightweight soft error mitigation techniques to embedded mixed precision deep neural networks

Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs' precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers

SOFIA: An automated framework for early soft error assessment, identification, and mitigation

The occurrence of radiation-induced soft errors in electronic computing systems can either affect non-essential system functionalities or violate safety-critical conditions, which might incur life-threatening situations. To reach high safety standard levels, reliability engineers must be able to explore and identify efficient mitigation solutions to reduce the occurrence of soft errors at the initial design cycle. This paper presents SOFIA, a framework that integrates: (i) a set of fault injection techniques that enable bespoke inspections, (ii) machine learning methods to correlate soft error results and system architecture parameters, and (iii) mitigation techniques, including: full and partial triple modular redundancy (TMR) as well as a register allocation technique (RAT), which allocates the critical code (e.g., application’s function, machine learning layer) to a pool of specific processor registers. The proposed framework and novel variations of the RAT are validated through more than 1739k fault injections considering a real Linux kernel, benchmarks from different domains and a multi-core Arm processor.</p

Efficient Embedded Software Migration towards Clusterized Distributed-Memory Architectures

A large portion of existing multithreaded embedded sofware has been programmed according to symmetric shared memory platforms where a monolithic memory block is shared by all cores. Such platforms accommodate popular parallel programming models such as POSIX threads and OpenMP. However with the growing number of cores in modern manycore embedded architectures, they present a bottleneck related to their centralized memory accesses. This paper proposes a solution tailored for an efficient execution of applications defined with shared-memory programming models onto on-chip distributed-memory multicore architectures. It shows how performance, area and energy consumption are significantly improved thanks to the scalability of these architectures. This is illustrated in an open-source realistic design framework, including tools from ASIC to microkernel

Impact of radiation-induced soft error on embedded cryptography algorithms

With the advance of autonomous systems, security is becoming the most crucial feature in different domains, highlighting the need for protection against potential attacks. Mitigation of these types of attacks can be achieved using embedded cryptography algorithms, which differ in performance, area, and reliability. This paper compares hardware implementations of the eXtended Tiny Encryption Algorithm (XTEA) and the Advanced Encryption Standard (AES) algorithms. Results show that the XTEA implementation gives the best relative performance (e.g., throughput, power), area, and soft error reliability trade-offs

Soft error assessment of attitude estimation algorithms running in a resource-constrained device under neutron radiation

This paper assesses the soft error reliability of attitude estimation algorithms running on a resource-constrained microprocessor under neutron radiation. Results suggest that the EKF algorithm has the best trade-off between reliability and runtime overhead.</p

A lightweight mitigation technique for resource-constrained devices executing DNN inference models under neutron radiation

Deep neural network (DNN) models are being deployed in safety-critical embedded devices for object identification, recognition, and even trajectory prediction. Optimised versions of such models, in particular the convolutional ones, are becoming increasingly common in resource-constrained edge-computing devices (e.g., sensors, drones), which typically rely on reduced memory footprint, low power budget and low-performance microprocessors. DNN models are prone to radiation-induced soft errors, and tackling their occurrence in resource-constrained devices is a mandatory and substantial challenge. While traditional replication-based soft error mitigation techniques will likely account for a reasonable performance penalty, hardware solutions are even more costly. To undertake this almost contradictory challenge, this work evaluates the efficiency of a lightweight software-based mitigation technique, called Register Allocation Technique (RAT), when applied to a convolutional neural network (CNN) model running on two commercial Arm microprocessors (i.e., Cortex-M4 and M7) under the effects of neutron radiation. Gathered results obtained from two neutron radiation campaigns suggest that RAT can reduce the number of critical faults in the CNN model running on both Arm Cortex-M microprocessors. Results also suggest that the SDC FIT rate of the RAT-hardened CNN model can be reduced in up to 83% with a runtime overhead of 32%

Evaluation of the soft error assessment consistency of a JIT‐based virtual platform simulator

Soft error resilience has become an essential design metric in electronic computing systems as advanced technology nodes have become less robust to high-charged particle effects. Designers, therefore, should be able to assess this metric considering several software stack components running on top of commercial processors, early in the design phase. With this in mind, researchers are using virtual platform (VP) frameworks to assess this metric due to their flexibility and high simulation performance. In this regard, herein, this goal is achieved by analysing the soft error consistency of a just-in-time fault injection simulator (OVPsim-FIM) against fault injection campaigns conducted with event-driven simulators (i.e. more realistic and accurate platforms) considering single and multicore processor architectures. Reference single-core fault injection campaigns are performed on RTL descriptions of Arm Cortex-M0 and M3 processors, while gem5 simulator is used to multicore Arm Cortex-A9 scenarios. Campaigns consider different open-source and commercial compilers as well as real software stacks including FreeRTOS/Linux kernels and 52 applications. Results show that OVPsim-FIM is more than 1000× faster than cycle-accurate simulators and up to 312× faster than event-driven simulators, while preserving the soft error analysis accuracy (i.e. mismatch below to 10%) for single and multicore processors